Vertically stacked integrated circuits, with multiple dies interconnected vertically via through silicon vias (TSVs), are one kind of 3D integration circuit technology, which provide vertical stacking of two or more dies with a dense, high-speed interface. The global wire length is reduced by a factor of the square root of the number of layers used, leading to performance improvement and power reduction of the interconnection. Thus, three-dimensional integration technology is a promising technology in providing a dense and high-speed communication interface to achieve high performance with low transmission power.
FIG. 1 shows a conceptual structure of a 3D stacked multichip package 100 using TSVs in flip-chip packaging technology. In the exemplary structure, four layers of chips or dies 110-140 are stacked successively on top of a package substrate 150 with multiple micro-connects 160. Through-silicon-via (TSV) 170 is used for passing both electrical and power signals. Power is delivered from an off-chip voltage regulator (not shown), through controlled-collapse-chip-connection (C4) bumps 180 to the bottom die 110, then to the upper dies 120-140 via TSV 170. A thermal interface material 190, heat sink 191 and heat spreader 192 are disposed over die 140 successively.
Often, a 3D stacked chip is powered by a power delivery system constituted of two parts, commonly known as off-chip paths and on-chip networks. The off-chip paths refer to the power delivery path from voltage source and/or package substrate to a chip. The on-chip network refers to the R(L)C network inside a chip, which usually comprises parasitic resistance, inductance in the delivery path and decoupling capacitance for eliminating transient voltage noise. A simplified circuit model of such a power delivery network to a 3D stacked multichip package is shown in FIG. 2, wherein power delivery system 200 for a 3D stacked multichip package comprises off-chip paths 210 and on-chip networks 220, both of them being marked by dotted boxes as shown in FIG. 2. The off-chip paths 210 deliver power from a voltage source to the 3D on-chip networks 220 via bumps 230.
Despite the promising features of rapid data transferring across layers, low transmission power and high device density, 3D integration techniques also confront many challenges, one of which is power supply noise. By stacking multiple dies vertically, 3D chips have higher load than the same-sized 2D chips, leading to larger voltage droop due to imperfect parasitic impedance of the power delivery network (PDN) and current fluctuation of circuits, damaging power integrity. Power integrity issues may cause timing failures, thereby degrading the system reliability.